library verilog;
use verilog.vl_types.all;
entity sx_register is
    port(
        clk             : in     vl_logic;
        din             : in     vl_logic_vector(3 downto 0);
        dout            : out    vl_logic_vector(3 downto 0);
        s0              : in     vl_logic;
        s1              : in     vl_logic;
        rst             : in     vl_logic
    );
end sx_register;
